RegViz: Visualize IFRCST

Silicon Labs /SiM3_NRND /SIM3U166_B /EMIF_0 /IFRCST_1

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Interpret as IFRCST_1

ALERDH=LOW, CSRDH=LOW, ALERAH=LOW, OERDW=LOW, WRRDW=LOW, CSRAS=LOW, OERAH=LOW, OERDH=LOW, CSRAH=LOW, WRRDH=LOW, ALERDW=LOW, OERAS=LOW, WRRAH=LOW, ALERAS=LOW, CSRDW=LOW, WRRAS=LOW

Description

Interface Read Control States

Fields

CSRAS	Chip Select Read Address Setup State. 0 (LOW): Set chip select (CSx) to low during the read address setup state. 1 (HIGH): Set chip select (CSx) to high during the read address setup state.
CSRAH	Chip Select Read Address Hold State. 0 (LOW): Set chip select (CSx) to low during the read address hold state. 1 (HIGH): Set chip select (CSx) to high during the read address hold state.
CSRDW	Chip Select Read Data Wait State. 0 (LOW): Set chip select (CSx) to low during the read data wait state. 1 (HIGH): Set chip select (CSx) to high during the read data wait state.
CSRDH	Chip Select Read Data Hold State. 0 (LOW): Set chip select (CSx) to low during the read data hold state. 1 (HIGH): Set chip select (CSx) to high during the read data hold state.
OERAS	Output Enable Read Address Setup State. 0 (LOW): Set output enable (/OE) to low during the read address setup state. 1 (HIGH): Set output enable (/OE) to high during the read address setup state.
OERAH	Output Enable Read Address Hold State. 0 (LOW): Set output enable (/OE) to low during the read address hold state. 1 (HIGH): Set output enable (/OE) to high during the read address hold state.
OERDW	Output Enable Read Data Wait State. 0 (LOW): Set output enable (/OE) to low during the read data wait state. 1 (HIGH): Set output enable (/OE) to high during the read data wait state.
OERDH	Output Enable Read Data Hold State. 0 (LOW): Set output enable (/OE) to low during the read data hold state. 1 (HIGH): Set output enable (/OE) to high during the read data hold state.
WRRAS	Write Signal Read Address Setup State. 0 (LOW): Set write signal (/WR) to low during the read address setup state. 1 (HIGH): Set write signal (/WR) to high during the read address setup state.
WRRAH	Write Signal Read Address Hold State. 0 (LOW): Set write signal (/WR) to low during the read address hold state. 1 (HIGH): Set write signal (/WR) to high during the read address hold state.
WRRDW	Write Signal Read Data Wait State. 0 (LOW): Set write signal (/WR) to low during the read data wait state. 1 (HIGH): Set write signal (/WR) to high during the read data wait state.
WRRDH	Write Signal Read Data Hold State. 0 (LOW): Set write signal (/WR) to low during the read data hold state. 1 (HIGH): Set write signal (/WR) to high during the read data hold state.
ALERAS	Address Latch Enable Read Address Setup State. 0 (LOW): Set address latch enable (ALEm) to low during the read address setup state. 1 (HIGH): Set address latch enable (ALEm) to high during the read address setup state.
ALERAH	Address Latch Enable Read Address Hold State. 0 (LOW): Set address latch enable (ALEm) to low during the read address hold state. 1 (HIGH): Set address latch enable (ALEm) to high during the read address hold state.
ALERDW	Address Latch Enable Read Data Wait State. 0 (LOW): Set address latch enable (ALEm) to low during the read data wait state. 1 (HIGH): Set address latch enable (ALEm) to high during the read data wait state.
ALERDH	Address Latch Enable Read Data Hold State. 0 (LOW): Set address latch enable (ALEm) to low during the read data hold state. 1 (HIGH): Set address latch enable (ALEm) to high during the read data hold state.

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